DK-DEV-5SGXEA7N【PDF 145/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51006

2014.01.10

OCT Calibration in User Mode

5-33

When ENAOCT is 1, all OCT calibration blocks are in calibration mode. When ENAOCT is 0, all OCT calibration

blocks are in serial data transfer mode. The OCTUSRCLK clock frequency must be 20 MHz or less.

Note: You must generate all user signals on the rising edge of the OCTUSRCLK signal.

Figure 5-13: OCT User Mode Signal — Timing Waveform for One OCT Block

This figure shows the user mode signal-timing waveforms.

OCTUSRCLK

ENAOCT

nCLRUSR

Calibration Phase

ENASER0

1000 OCTUSRCLK Cycles

32

OCTUSRCLK

Cycles

ts2 p

ts2p ≥ 25 ns

S2PENA_1A

OCT Calibration

To calibrate OCT block N (where N is a calibration block number), you must assert ENAOCT one cycle before

asserting ENASER N . You must also set nCLRUSR low for one OCTUSRCLK cycle before the ENASER N signal is

asserted. Assert the ENASER N signals for 1,000 OCTUSRCLK cycles to perform R S OCT and R T OCT calibration.

You can deassert ENAOCT one clock cycle after the last ENASER is deasserted.

Serial Data Transfer

After you complete calibration, you must serially shift out the 32 bit OCT calibration codes (16 bit R S OCT

and 16 bit R T OCT) from each OCT calibration block to the corresponding I/O buffers. Only one OCT

calibration block can send out the codes at any time by asserting only one ENASER N signal at a time. After

you deassert ENAOCT , wait at least one OCTUSRCLK cycle to enable any ENASER N signal to begin serial transfer.

To shift the 32 bit code from the OCT calibration block N , you must assert ENASER N for exactly 32 OCTUSRCLK

cycles. Between two consecutive asserted ENASER signals, there must be at least one OCTUSRCLK cycle gap, as

shown in the preceding figure.

After calibrated codes are shifted in serially to each I/O bank, the calibrated codes must be converted from

serial to parallel format before being used in the I/O buffers. The preceding figure shows the S2PENA signals

that can be asserted at any time to update the calibration codes in each I/O bank. All I/O banks that received

the codes from the same OCT calibration block can have S2PENA asserted at the same time, or at a different

time, even while another OCT calibration block is calibrating and serially shifting codes. The S2PENA signal

is asserted one OCTUSRCLK cycle after ENASER is deasserted for at least 25 ns. You cannot use I/Os for

transmitting or receiving data when their S2PENA is asserted for parallel codes transfer.

I/O Features in Stratix V Devices

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